The present invention relates to the electrical, electronic, and computer arts, and, more particularly, to methods for forming FinFETs.
Multi-gate field-effect transistors (FETs) are of considerable interest because of their superior electrostatic integrity, as well as their promise of lower supply voltages, reduced threshold voltages, and extended scalability. FinFETs are one form of such multi-gate device. In a FinFET, a narrow channel feature (i.e., fin) is raised above the substrate and passes under a gate, which effectively wraps around the fin. The gate is thereby capacitively coupled to the top as well as the sides of the fin. So structured, very little leakage current passes through channel portions of the fin when the device is in the off state. This allows the use of lower threshold voltages and higher switching speeds.
The inclusion of strained channels in modern FinFETs holds the promise of increased charge carrier mobilities and transistor device currents. Unfortunately, however, electron mobility and hole mobility benefit from different strain characteristics. The performance of an n-type FinFET is typically improved if its channel is tensily strained. In contrast, the performance of a p-type FinFET is typically improved if its channel is compressively strained. The two types of FinFETs thereby benefit from opposite strain conditions, adding complexity to any fabrication methodologies that wish to take advantage of strain characteristics.